Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit often includes complementary metal oxide semiconductor (CMOS) field effect transistors (FET).
Conventional transistors are generally comprised of gates disposed between drain and source regions. The drain and source regions are typically located within a semiconductor film or substrate, and the gates are provided on a top surface of film or substrate. The drain and source regions can be heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a shallow or thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions, as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in bulk semiconductor substrate during ion implantation can cause the dopant to diffuse more easily (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
Heretofore, CMOS processes have required furnace anneal processes, rapid thermal anneal (RTA) processes, and spike RTA processes to temporarily heat the substrate. The heating processes are required to diffuse and to activate dopants in polysilicon gate materials, in the source region, and in the drain region. Additionally, heating processes are also utilized during the deposition of certain materials, the silicidation of metals, and other fabrication steps. The heating processes significantly increase the thermal budget of the CMOS process. For example, even spike RTA processes subject the substrate to at least one second of high temperature treatment (e.g., over 900.degree. C.).
The total thermal budget dopants experienced by the IC becomes more critical as transistors become smaller. For example, dopants in the source region, drain region, and gate region diffuse more readily in response to high temperatures. Accordingly, high temperatures can adversely affect ultra-shallow junction formation, the formation of ultra-tight dopant profiles for halo implants and retrograde channel implants, and dopant penetration into the gate (boron penetration into the gate of a P-channel transistor). Ultra-shallow junctions and tight profile pocket regions improve immunity to short-channel effects, such as, threshold voltage roll-off. Short-channel effects are a major barrier to appropriate transistor scaling.
Thus, there is a need for a method of manufacturing a transistor that does not utilize a conventional annealing process step. Further still, there is a need for transistors that can be manufactured within a low thermal budget. Even further still, there is a need for an efficient method of manufacturing source and drain extensions that minimizes ion implantation channeling effect.